With the miniaturization of electronic devices and increasing circuit density in semiconductor industry, chip size package (CSP) is developed, where the package size is similar to the semiconductor chip encased within the package. Conventional packaging technologies, wire bonding, tape automatic bonding (TAB) and flip chip, have their own disadvantages. In wire bonding and TAB, a semiconductor package has a footprint much larger than that of the primitive chip. Flip chip package involves a direct electrical connection of face down electronic components onto substrates/carriers via conductive solder balls/bumps of the chip. The flip-chip package encounters a problem, namely, cracking of solder ball joint due to large thermal expansion mismatch between a wafer and a substrate. Chip size package is manufactured either in the form of individual chips diced from a wafer, or in a wafer form and then the individual chip size packages are singulated from the wafer. The latter is referred to as a wafer level chip size package (hereinafter WLCSP). For WLCSP, generally a plurality of compatible pads formed in a peripheral arrayed type on semiconductor chips are redistributed through conventional redistribution processes involving a redistribution layer into a plurality of metal pads, sometimes called solder bumps, in an area array type. The solder bumps on a WLCSP surface are much larger in diameter and much farer inbetween, and the printed circuit board assembly of a WLCSP is more robust. This kind of WLCSP technique has superior electrical performance and lower manufacturing costs than other packaging types, so it will play an important role in the production of future electronics.
Shellcase Co. Israel developed its unique and advanced WLCSP technology, classified ShellOP, ShellOC, and ShellUT, to package optical and image sensors, e.g., charge-coupled devices (CCD) and/or CMOS imagers integrated on a silicon wafer. Currently, CCD and CMOS imagers are explosively used in electronic products. Unlike many packaging methods, the Shellcase process requires no lead frames, or wire bonding. Briefly, ShellOP utilizes a glass/silicon/glass sandwich structure to enable image-sensing capabilities through the actual packaging structure and to protect the sensors from being contaminated by external environment. ShellOC adopts the same sandwich structure, but extra cavities are configured on a first glass which is bonded to a silicon wafer with integrated circuits on for accommodating the above imagers. Also, cavities enable the use of micro-lenses for enhanced image quality. ShellOC is thus the packaging solution of choice for image sensors with micro-lenses. In the ShellUT package, cavities are still kept but a second glass is removed so that the associated package height is reduced. It is expected that ShellUT package should be a mainstream technology among Shellcase type packaging technology in the future. U.S. Pat. Nos. 6,646,289, 6,777,767 and 6,972,480 are considered to be relevant.
FIG. 1 is a typical cross-section of prior art ShellOC packaged chip device with a one-layer lead structure and T-shape junction thereof. As shown in FIG. 1, a first/top glass 5 with cavity walls 10 thereon covers compatible pads 15 furnished silicon chip 20. An epoxy 25 is used to bond a second/bottom glass 30 to the chip 20 on which a portion of compatible pads have been exposed before by means of photolithography and plasma etching techniques. After a barrier solder mask 35 is coated on the glass 30, notching is performed so that inverted leads 40, via sputtering deposition, connect electrically to the compatible pads 15 in the form of so-called T-shape junction as marked by circle. The leads 40 are coated with a protective solder mask 45 thereon. The solder-mask 45 is a dielectric material that electrically isolates the leads 40 from external contact, and protects the lead surface against corrosion. Solder bumps 50 are attached to the bottom end of leads 45, and are suitable for printed circuit board (PCB) mounting by known methods. Solder bumps 50 may be formed by known methods such as screen printing, and may be suitably shaped for PCB mounted.
In the foregoing Shellcase type WLCSP technology, a one-layer lead is only incorporated in a whole package process, therefore, the quantity of per area of compatible pads is limited due to limited space for layout of lead on the chip bottom surface.